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Implementation of 8085 Microprocessor Arithmetic Logic Unit in Field Programmable Gate Array (FPGA) Using Vedic Mathematics
Last modified: 2021-11-22
Abstract
Abstract. The Arithmetic Logic Unit (ALU) is an important part of the microprocessor that performs arithmetic and logic instructions. The performance of the microprocessor heavily depends on the performance of the ALU. In this paper, ALU is designed using vedas mathematical concepts to optimize design complexity and speed in arithmetic units, namely the Urdhva-tiryagbhyam Sutra and the Nikhilam Sutra. The proposed project is coded in Very High-Speed Integrated Circuit Hardware Description Language (VHDL), followed by synthesization using EDA tool, Xilinx ISE Design Suite 14.7, and implemented in Spartan-3E FPGA. The results of the proposed project will be compared with other methods to determine the effectiveness of the use of the vedas mathematical method.
References
Chetan B V, Arpitha H V and Vishwanath Meghana 2016 Fpga implementation of alu using vedic mathematics Proceedings of 2016 IOSR Journal of VLSI and Signal Processing, IOSR-JVSP 2016 pp 08-12
Woods R, McAllister J, Lightbody G and Yi Y 2017 Implementation of signal processing systems second edition (New Jersey: John Wiley & Sons)
Rawat G, Rathore K, Goyal S, Kala S and Mittal P 2015 Design and analysis of alu: vedic mathematics approach Proceedings of International Conference on Computing, Communication and Automation, ICCCA 2015 pp 1372-1376
Jain S, Pancholi M, Garg H and Saini S 2014 Binary division algorithm and high speed deconvolution algorithm (based on ancient indian vedic mathematics) Proceedings of 11th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2014 pp 01-05
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